1. Field of the Invention
This application relates generally to fabricating integrated circuits, and more particularly to a process for forming an epitaxial channel vertical MOS device.
2. Description of the Related Art
Conventional thin film processing techniques are now commonly used to produce integrated circuits. These integrated circuits may incorporate various devices, including transistors. A common type of transistor uses a gate that is insulated from a channel in which conduction between the transistor source and drain may occur dependent upon the gate to source voltage. Particularly, appropriate biasing creates an electrical field that attracts charge carriers into the channel which then provides a conductive path between the source and drain. Such a transistor may be referred to as a Metal-Oxide-Semiconductor Field Effect Transistor, or MOSFET. Notably, metal refers to the gate, which may also be non-metallic but is generally conductive, and oxide refers to the insulating layer between the gate and the channel, which insulating layer may or may not include oxide.
Ever increasing scales of integration mandate the inclusion of a corresponding number of transistors on a single chip. The demand for greater numbers of transistors, in turn, requires closer spacing in order to allow their inclusion in a finite amount of space. An important dimension in the fabrication of semiconductor devices, such as transistors, is the length of the channel. The length of the channel affects transistor operation, and impacts the number of transistors that can be provided in a given space. It is therefore desirable to minimize the channel size and to provide consistent channel dimensions and characteristics when fabricating integrated circuits.
Other concerns in the fabrication of integrated circuits are the provision of source and drain regions that do not have high resistivity, particularly for low voltage applications, where high resistivity in the source/drain regions prevents proper operation. Also, it is desirable to retain control of the resistivity of the source and drain regions during fabrication, so that produced transistors can have substantially equal source and drain resistivity, facilitating symmetrical operation (i.e., interchangeable source and drain regions).
Many typical MOSFET transistors include a source, drain and channel that can be said to be coplanar since they reside in a common horizontal plane. Since these source and drain regions are located at the same level in the substrate, their features may be similarly controlled during fabrication. Indeed, the source and drain regions are often formed in a common processing step. Thus, fabricating horizontal transistors having symmetry is relatively simple.
A vertical transistor includes a drain (or source) region that has a greater depth within the substrate than does its source (or drain) region, as well as an intervening channel. The source, drain and channel are generally arranged in a vertical direction. This arrangement can be advantageous because it consumes less substrate surface area than horizontal arrangements. Also, the vertical transistor can provide a transistor having a channel length that is smaller than that which could be produced for the horizontal type, which is more directly limited by the minimum photolithographic resolution. Thus, it may be more desirable to implement vertical transistors for increasing scales of integration.
Certain aspects of conventional vertical transistors, however, remain problematic. For one, fabrication of vertical transistors having symmetry and corresponding interchangeable source and drain regions remains difficult, particularly in that it is difficult to dictate the features of the deeper doped region (e.g., the drain). Additionally, although smaller channel lengths are generally provided by the vertical transistor, the length of the channel is not as consistent as would be desired. Finally, the deeper doped region tends to have high resistivity, which can prevent proper operation, particularly in low power environments.
Thus, there remains a need for a vertical transistor with a minimized, consistent channel length, and source/drain regions having low resistivity and symmetry.